1. Field of the Invention
The present invention relates to a circuit board and the method of manufacturing the circuit board, and a circuit device and a method of manufacturing the circuit device. In particular, the present invention relates to a circuit board having a structure in which wirings formed on a main surface of a substrate are covered with a cover layer, and a method of manufacturing the circuit board. Moreover, the present invention also relates to a circuit device provided with such a circuit board and a method of manufacturing the circuit device.
2. Description of the Related Art
Electronic equipments such as cellular phones have been reduced in size, and have been made to include enhanced functionality. Along with such development, most circuit devices housed in such electronic equipments include fine wirings. A circuit device with a circuit board 107 will be described below with reference to FIG. 16. This technology is described for instance in Japanese Patent Application No. 2003-324263.
As shown in FIG. 16, a circuit device 100 has a structure in which a circuit element (semiconductor element 105) is mounted on a first wiring layer 102A formed in the upper surface of the circuit board 107.
The circuit board 107 includes a substrate 101 made of resin such as glass epoxy, and wiring layers formed on the upper and bottom surfaces of the substrate 101. Specifically, the first wiring layer 102A and a second wiring layer 102B are formed on the upper surface of the substrate 101. The first wiring layer 102A is placed on the second wiring layer 102B with an insulating layer 103 interposed therebetween. In addition, on the bottom surface of the substrate 101, third and fourth wiring layers 102C and 102D are stacked in a manner that the fourth wiring layer 102D is placed under the third wiring layer 102C with a different insulating layer 103 interposed therebetween. The first and second wiring layers 102A and 102B are connected to each other at predetermined positions with connection portions 104 provided so as to penetrate the insulating layer 103, while the third and fourth wiring layers 102C and 102D are connected to each other at predetermined positions with different connection portions 104 provided so as to penetrate the different insulating layer 103. Moreover, the second and third wiring layers 102B and 102C are connected to each other at predetermined positions with still different connection portions 104 provided so as to penetrate the substrate 101. Here, the thickness of the circuit board 107 is approximately 1 mm, for example.
The first wiring layer 102A, which is the uppermost wiring layer, is covered with a cover layer 109, and electrical connection regions (the parts to each of which a thin metallic wire 108 is to be connected) of the first wiring layer 102A are exposed from openings formed by removing parts of the cover layer 109. Here, the cover layer 109 is made of a resin material such as epoxy resin.
On the upper surface of the cover layer 109, the semiconductor element 105 is adhered. Here, the semiconductor element 105 is adhered at its bottom surface to the cover layer 109 by using an insulating adhesive or the like. Electrodes provided on the upper surface of the semiconductor element 105 are electrically connected to the first wiring layer 102A through the thin metallic wires 108.
Moreover, the upper surface of the circuit board 107 is covered with a sealing resin 106 so that the sealing resin 106 can cover the semiconductor element 105 and the thin metallic wires 108.
A manufacturing method of the circuit board 107 having the above-described structure is as follows. Firstly, the second wiring layer 102B and the third wiring layer 102C are formed respectively on the upper surface and the bottom surface of the substrate 101 made of a resin material such as epoxy resin. These wiring layers are formed by means of the etching of conductive films adhered on the upper and bottom surfaces of the substrate 101, or a plating process performed selectively on the upper and bottom surfaces of the substrate 101. Then, the connection portions 104 that penetrate the substrate 101 are formed to connect the second wiring layer 102B and the third wiring layer 102C. Thereafter, the second and third wiring layers 102B and 102C are covered with the insulating layers 103, respectively On surfaces of the respective insulating layers 103, the first wiring layer 102A and the fourth wiring layer 102D are formed. The forming method of the first and fourth wiring layers 102A and 102D are same as that of the second and third wiring layers 102B and 102C described above. Then, the connection portions 104 that penetrate the corresponding insulating layer 103 are formed to connect the first wiring layer 102A and the second wiring layer 102B. Thereafter, the cover layer 109 is formed so as to cover the first wiring layer 102A, which is the uppermost wiring layer, and then is partially removed to form openings so that the electrical connection regions of the first wiring layer 102A can be exposed from the openings to the outside.
However, the circuit device 100 having the above-described structure has a problem that the adhesion between the first wiring layer 102A, which is the uppermost wiring layer, and the cover layer 109 is insufficient. Specifically, as the size of the circuit integrated on the semiconductor element 105 increases, the calorific value attributable to the operation of the semiconductor element 105 also increases. As a result, thermal stress occurs at the interface between the first wiring layer 102A and the cover layer 109 since the thermal expansion coefficient of the first wiring layer 102A made of a metal such as copper is significantly different from that of the cover layer 109 made of resin. If thermal stress is applied to the interface of the layers 102A and 109 a large number of times, the cover layer 109 may be exfoliated from the first wiring layer 102A.
Japanese Patent Application Publication No. 2002-76610 discloses a method to solve the above-described problem. The technical features of this Publication will be described below with reference to FIG. 17. As shown in FIG. 17, a conductor circuit 111 is formed on the upper surface of an insulating circuit board 110. In addition, surfaces of the conductor circuit 111 are uniformly roughened in order to prevent the problem attributable to the difference between the thermal difference coefficients of the conductor circuit 111 and the insulating resin portion.
Specifically, in Japanese Patent Application Publication No. 2002-76610, etching solution including hydrogen peroxide water, sulfuric acid, tetrazole and the like, is used for patterning for the conductor circuit 111, to form the conductor circuit 111 with the above-described structure. In the etching process, compounds 112 attach to the surfaces of the conductor circuit 111 through this patterning. As a result, etching progresses evenly from the surfaces, excluding the portions to which the compounds 112 are attached, of the conductor circuit 111, so that the surfaces of the conductor circuit 111 are uniformly roughened. According to this Publication, with such uniformly roughened surfaces, the adhesion strength between the conductor circuit 111 and the resin portion can be increased, and hence, the problem of exfoliation of the conductor circuit 111 and the resin portion can be avoided.
However, the technical features disclosed in Japanese Patent Application Publication No. 2002-76610 lead to a problem that the conductor circuit 111 is exfoliated from a solder resist. FIG. 18A is a cross-sectional view showing a region around the conductor circuit 111, and FIG. 18B is a cross-sectional view showing a state in which a cover layer 114 (solder resist) is exfoliated from the conductor circuit 111.
As shown in FIG. 18A, the conductor circuit 111 is formed on the upper surface of the circuit board 110, and end portions (shown in FIG. 18 is the right end portion) of the conductor circuit 111 are each covered with a plating film 112 formed by means of electroplating. Moreover, the cover layer 114 made of a resin material is formed so as to cover the upper surfaces of the conductor circuit 111 and the circuit board 110. While covering the upper surface of the conductor circuit 111, the cover layer 114 also covers part of surfaces of the plating films 112.
The phenomenon of the exfoliation of the cover layer 114 thus formed will be described with reference to FIG. 18B. As described above, since the thermal expansion coefficient of the conductor circuit 111 is different from that of the cover layer 114, thermal stress occurs at the interface between the conductor circuit 111 and the cover layer 114 each time the temperature changes. Here, the thermal stress is large at the end portions of the cover layer 114. As shown in FIG. 18B, the amount of aforementioned thermal stress F1, which is the stress occurs around the inner part of the cover 114 (on the left side in FIG. 18B), is small, while the amount of aforementioned thermal stress F2, which is the stress occurs around the end portions of the cover layer 114, is relatively large. In addition, the overall adhesion strength between the conductor circuit 111 and the cover layer 114 is approximately the same, since the roughness degree is approximately the same across the surfaces of the conductor circuit 111.
Due to the above, in the peripheral region of the circuit board 110, large thermal stress is applied to the interface between the conductor circuit 111 and the cover layer 114 each time the temperature changes. As a result, a problem arises, in this region, that the cover layer 114 is exfoliated from the conductor circuit 111. If the cover layer 114 is exfoliated, moisture ingress is likely to occur at the interface, and hence, the moisture resistance is deteriorated.